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CD4019BC Quad AND-OR Select Gate
October 1987 Revised April 2002
CD4019BC Quad AND-OR Select Gate
General Description
The CD4019BC is a complementary MOS quad AND-OR select gate. Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors. These complementary MOS (CMOS) transistors provide the building blocks for the 4 "AND-OR select" gate configurations, each consisting of two 2-input AND gates driving a single 2-input OR gate. Selection is accomplished by control bits KA and KB. All inputs are protected against static discharge damage.
Features
s Wide supply voltage range: s Low power TTL compatibility: or 1 driving 74LS 3.0V to 15V Fan out of 2 driving 74L s High noise immunity: 0.45 VDD (typ.)
Applications
* AND-OR select gating * Shift-right/shift-left registers * True/complement selection * AND/OR/EXCLUSIVE-OR selection
Ordering Code:
Order Number CD4019BCM CD4019BCN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Top View
(c) 2002 Fairchild Semiconductor Corporation
DS005952
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CD4019BC
Schematic Diagram
Schematic diagram for 1 of 4 identical stages
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CD4019BC
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C (Note 3) 700 mW 500 mW
Recommended Operation Conditions (Note 2)
DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA)
-0.5V to +18V -0.5V to VDD +0.5V -65C to +150C
+3V to +15V
0V to VDD V
-55C to +125C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics
Symbol IDD Parameter Quiescent Device Current VOL LOW Level Output Voltage VDD = 5V VDD = 10V VDD = 15V |IO| < 1 A VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level Output Voltage |IO| < 1 A VDD = 5V VDD = 10V VDD = 15V VIL LOW Level Input Voltage VIH HIGH Level Input Voltage IOL LOW Level Output Current (Note 4) IOH HIGH Level Output Current (Note 4) IIN Input Current
Conditions
-55C Min Max 0.25 0.5 1.0 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.64 1.6 4.2 -0.25 -0.62 -1.8 -0.1 0.1 3.5 7.0 11.0 0.51 1.3 3.4 -0.2 -0.5 -1.5 4.95 9.95 14.95 Min
+25C Typ 0.25 0.5 1.0 0 0 0 5 10 15 2 4 6 3 6 9 1 2.5 10 -0.4 -1.0 -3.0 -10-5 10-5 -0.10 0.10 1.5 3.0 4.0 Max 1 2 4 0.05 0.05 0.05
+125C Min Max 7.5 15 30 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.36 0.9 2.4 -0.14 -0.35 -1.1 -1.0 1.0
Units
A
V
V
VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V
V
V
mA
mA
A
Note 3: VSS = 0V unless otherwise specified. Note 4: IOH and IOL are tested one output at a time.
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CD4019BC
AC Electrical Characteristics
Symbol tPHL, tPLH tTHL Parameter Propagation Delay, Input to Output HIGH-to-LOW Level Transition Time tTLH LOW-to-HIGH Level Transition Time CIN Input Capacitance
(Note 5)
Conditions Min Typ 100 50 45 100 50 40 150 70 50 5 10 Max 300 120 100 200 100 80 300 140 100 7.5 15 pF ns ns ns Units
TA = 25C, CL = 50 pF, RL = 200k, unless otherwise specified VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V All A and B Inputs KA and KB Inputs
Note 5: AC Parameters are guaranteed by DC correlated testing.
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CD4019BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
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CD4019BC Quad AND-OR Select Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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